The present invention relates to a driving circuit for signal lines formed in a semiconductor integrated circuit.
In recent years, so-called logic hybrid memories in which a semiconductor memory device (to be referred to as a memory hereinafter) and a logic integrated circuit (to be referred to as a logic hereinafter) are integrated on one chip are becoming popular. The following advantages can be obtained by integrating a memory and a logic on one chip.
(1) The memory and the logic can be encapsulated in one package although they are conventionally independently encapsulated in packages. For this reason, the packaging cost can be reduced.
(2) Since no package leads, bonding wires, and interconnections on the printed circuit board are present between the memory and the logic, the operating frequency can be raised.
(3) As the number of packages to be arranged on the printed circuit board decreases, the area of the printed circuit board can be reduced.
(4) A large data bus width (the number of data lines connecting the memory and the logic) can be realized although it is physically impracticable in the conventional structure in which the memory and the logic are independently encapsulated in packages and connected on a printed circuit board.
Because of the above advantages, the logic hybrid memories are becoming popular in the field of, e.g., graphics ICs which require high-speed transfer of a large quantity of data between the memory and the logic.
Generally, the data transfer rate between the memory and the logic is represented by the product of the operating frequency of the data bus and the data bus width. As described above, since the data bus width can be relatively easily increased in the logic hybrid memory, the data bus width tends to be larger to raise the data transfer rate between the memory and the logic. In days when the data bus width was as small as 64 data lines, the power consumed by the data bus was negligible relative to the power consumption of the entire logic hybrid memory. However, the wider the data bus is, the larger the power consumption of the data bus becomes. It can be readily imagined that, in the near future, chips cannot be encapsulated in plastic packages poor in heat resistance because of heat generated by the power consumed by the data bus, or chips erroneously operate due to noise generated by the charge/discharge current of the data bus.
When the operating frequency is f (Hz), the capacitance per data bus is C (F), and the amplitude (potential difference between "H" and "L") on the data bus is V (V), power P (W) consumed by the data bus is given by: EQU P=N.multidot.f.multidot.C.multidot.V.sup.2 ( 1)
To decrease the power consumption P, the data bus width (N) may be reduced, the capacitance (C) of the data bus may be decreased, or the amplitude (V) may be reduced.
However, since the data transfer rate is represented by the product of the data bus width (N) and the frequency (f), as described above, reduction of these values means degradation in data transfer capability. In addition, since the data bus capacitance (C) depending on the bus length is determined by layout, this value can hardly be made small. On the other hand, the amplitude on the data bus exponentially takes effect, so a very large power reduction effect can be obtained by decreasing the amplitude.
A known example of the logic hybrid memory having a small data bus amplitude is ""An Experimental 295 MHz CMOS 4K.times.256 SRAM Using Bidirectional Read/Write Shared Sense Amp and Self-Timed Pulsed Word-Line Drivers", in IEEE Journal of Solid-State Circuits, vol. 30, No. 11, November 1995" by the present inventor.
The static random access memory (SRAM) described in this paper has 256 pairs of complementary data buses. FIG. 18 shows an equivalent circuit of the data bus driving circuit of this SRAM. Reference symbol OUT denotes a signal for driving the output circuit of the DRAM. Reference numeral 71 denotes an inverter for inverting the signal OUT; 72 and 73, p-channel MOS transistors; and 74, a data bus. Reference numeral DATA denotes a signal output onto the data bus 74; VDD, a power supply (e.g., 3.3 V) for supplying the "H"-side potential of the data bus 74; and VDDL, a power supply (e.g., 3.0 V) for supplying the "L"-side potential of the data bus 74. Reference numeral 75 denotes a parasitic capacitance 75 of the data bus 74.
The operation of the data bus driving circuit having the above arrangement will be described next with reference to a timing chart shown in FIG. 19. When a signal of "H" is to be output to the data bus 74, the signal OUT is set at the potential VDD. At this time, one MOS transistor 72 is turned on, and the other MOS transistor 73 is turned off. The data bus 74 is connected to the power supply potential VDD and set at a potential of 3.3 V.
When a signal of "L" is to be output to the data bus 74, the signal OUT is set at the ground potential. At this time, one MOS transistor 72 is turned off, and the other MOS transistor 73 is turned on. The data bus 74 is connected to the power supply potential VDDL and set at a potential of 3.0 V. Therefore, the amplitude on the data bus 74 is 3.3 V-3.0 V=0.3 V.
In this SRAM, the amplitude on the data bus 74 is as small as 0.3 V. For this reason, the power consumption of the data bus is decreased to approximately 1/60 that of the conventional SRAM whose data bus has an amplitude of 3.3 V equal to the power supply voltage. In the conventional DRAM having a data bus amplitude of 3.3 V, the power P consumed by the data bus is given by: EQU P=N.multidot.f.multidot.C.multidot.3.3.sup.2 =10.89N.multidot.f.multidot.C(2)
Since the SRAM described in this paper has complementary data buses, the number of data buses is N.times.2, and power P' consumed by all data buses is given by: EQU P'=2.times.N.multidot.f.multidot.C.multidot.0.3.sup.2 =0.18N.multidot.f.multidot.C (3)
The power consumption ratio is P:P'=60.5:1.
As is apparent from this evaluation result, when a small-amplitude data bus is used, power consumption of the data bus is largely decreased. However, in the SRAM described in the above paper, the intermediate power supply potential VDDL (3.0 V) on the "L" side of the data bus must be supplied from an external power supply.
In a general logic hybrid memory, the power supply voltage applied to the chip is 3.3 V or 5.0 V. It is cumbersome to independently prepare the power supply for the intermediate potential VDDL (3.0 V) for the "L"-side potential of the data bus, and additionally, the system cost increases.
In a general voltage drop circuit, a voltage drop is formed by dividing the power supply voltage by an appropriate resistor or the ON resistance of a transistor. In this scheme, however, some current must be flowed to the resistor or transistor to form the voltage drop, and the current is wastefully consumed by the resistor or transistor as Joule heat.